Tag: Hardware and Architecture
aLEAKator verifies masked hardware and software under leakage models
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What the study found The study presents aLEAKator, an open-source framework for automated formal verification of masked cryptographic accelerators and software on CPUs from HDL descriptions. It uses mixed-domain simulation to model leakage under several 1-probing leakage models, including robust and relaxed versions. Why the authors say this matters The authors say this matters because…
Hardware-efficient Mølmer–Sørensen gate performs comparably on superconducting hardware
What the study found A hardware-efficient implementation of the Mølmer–Sørensen gate was tested on superconducting quantum hardware and showed performance close to the device’s native controlled-NOT (CX) gate. The gate also produced the target Bell state from the |00⟩ input with a reported success probability of 94.2%. Why the authors say this matters The authors…
WaSC decouples WASM system access with low startup and memory use
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WaSC hardens WebAssembly sandboxes through system interface decoupling, achieving machine-level isolation while maintaining WASM performance advantages for serverless computing environments.
